1. Field of the Invention
The present invention relates to a semiconductor memory device and more specifically to a semiconductor memory device which uses ferroelectric capacitors or MTJ (Magnetic Tunnel Junction) devices.
2. Description of the Related Art
In recent years, a ferroelectric memory has received attention which has ferroelectric capacitors the dielectric layer of which is made of a ferroelectric material.
The ferroelectric memory utilizes the hysteresis property which is one of the properties of ferroelectric materials and stores data (“0” or “1”) through two different remanent polarization in a nonvolatile manner in a ferroelectric capacitor. To read the data, it is required to drive a plate line.
There has been a proposal for a memory cell array configuration of the ferroelectric memory in which two or more ferroelectric capacitors are connected to one cell transistor to allow a cross point type of memory cell array (see, for example, “A Quasi-Matrix Ferroelectric Memory for Future Silicon Storage” by Toshiyuki Nishihara et al, IEEE Journal of Solid State Circuits, Vol. 37, No. 11, Nov. 2002). This configuration can provide high integration density. In reading “1” in particular, however, electric fields will be produced between a bit line and nonselected plate line to disturb nonselected memory cells. As a result, data stored in the nonselected memory cells will suffer a deterioration in reliability.
In general, a combination of one cell transistor and one ferroelectric memory is known as a memory cell configuration of the ferroelectric memory. A method has been proposed by which such DRAM-type memory cells are arranged using folded bit lines to form a memory cell array and a selected memory cell itself is used as a reference potential generating cell (see, for example, “A Self-Reference Read Scheme for a 1T/1C FeRAM” by Junichi Yamada et al, 1998 Symposium on VLSI Circuits Digest of Technical Papers pp. 238–241. However, this memory cell array configuration is inferior in integration density to the previously described cross point type of memory cell array configuration.